(1) Pins FS1/MD, FS2/MC, SR/MS, CSEL (Schmitt-trigger input with internal pulldown, 3.3-V tolerant) (2) Pins SCKO1 (3) Pin XT1 (4) Pin XT2 (5) Jitter performance is specified as standard deviation of jitter for 27-MHz crystal oscillation and default SCKO frequency setting. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.Īll specifications 25☌, VDD1VDD3 VDD) = VCC = 27 MHz, crystal oscillation, = 48 kHz (unless otherwise noted) PARAMETER DIGITAL INPUT/OUTPUT Logic input VIH (1) VIL (1) IIH (1) IIL (1) VOH (2) VOL (2) Input logic level Input logic current Logic output Output logic level PLL1707 Sampling Sam ling frequency PLL1708 IOH 4 mA IOL 4 mA Standard fS Double fS Half fS Standard fS VIN = VDD VIN 0 V CMOS VDD 0.4 V kHz Vdc CMOS compatible 3.6 0.3 VDD 100 ☑0 Vdc ♚ TEST CONDITIONS MIN TYP MAX UNITĭouble 88.2 96 MASTER CLOCK (MCKO1, MCKO2) CHARACTERISTICS (fM = 27 MHz, = 15 pF, pF on measurement pin) Master clock frequency VIH VIL IIH IIL Input level(3) Input current(3) Output voltage (4) Output rise time Output fall time Duty cycle Clock jitter (5) Power-up time (6) PLL AC CHARACTERISTICS (SCKO0SCKO3) (fM = 27 MHz, pF on measurement pin) SCKO0 Fixed SCKO2 SCKO3 Output rise time Output fall time Output duty cycle Out ut system clock Output frequency PLL1708 PLL1707 Selectable for 48 kHz 384 fS Fixed Selectable for 48 kHz 80% of VDD 20% of VDD 80% of VDD 20% of VDD For crystal oscillation For external clock 45% VIN = VCC VIN 0 V MHz 26.73 0.7 VCC 0.3 VCC MHz V ♚ Vp-p ns
These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Package temperature (IR reflow, peak) 260☌ (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. Over operating free-air temperature range unless otherwise noted(1) PLL1705 AND PLL1706 Supply voltage: VCC, VDD1VDD3 Supply voltage differences: VCC, VDD1VDD3 Ground voltage differences: AGND, DGND1DGND3 Digital input voltage: FS1 (MD), FS2 (MC), SR (MS), CSEL Analog input voltage, XT1, XT2 Input current (any pins except supplies) Ambient temperature under bias Storage temperature Junction temperature Lead temperature (soldering) V to (VDD V to (VCC 5 s
#Multiclock erm power supply code
PRODUCT PACKAGE CODE OPERATION TEMPERATURE RANGE to 85☌ PACKAGE MARKING PLL1707 PLL1708 ORDERING NUMBER PLL1708DBQ PLL1708DBQR TRANSPORT MEDIA Tube Tape and reel Tube Tape and reel Production processing does not necessarily include testing of all parameters. Products conform to specifications per the terms of Texas Instruments standard warranty. PRODUCTION DATA information is current as of publication date. The PLL1707 and PLL1708 use the same die and they are electrically identical except for mode control. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ESD damage can range from subtle performance degradation to complete device failure. Failure to observe proper handling and installation procedures can cause damage. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. This integrated circuit can be damaged by ESD. The PLL1707 and PLL1708 are ideal for MPEG-2 applications which use a 27-MHz master clock such as DVD recorders, HDD recorders, DVD add-on cards for multimedia PCs, digital HDTV systems, and set-top boxes. The device gives customers both cost and space savings by eliminating external components and enables customers to achieve the very low-jitter performance needed for high performance audio DACs and/or ADCs. The clock outputs of the PLL1707 can be controlled by sampling frequency-control pins and those of the PLL1708 can be controlled through serial-mode control pins. The PLL1707 and PLL1708 can generate four system clocks from a 27-MHz reference input frequency. The PLL1707 and PLL1708 are low cost, phase-locked loop (PLL) multiclock generators. HDD + DVD Recorders DVD Recorders HDD Recorders DVD Players DVD Add-On Cards for Multimedia PCs Digital HDTV Systems Set-Top Boxes
FEATURES D 27-MHz Master Clock Input D Generated Audio System Clock (PLL1707):
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